Integrated circuits conventionally comprise a substrate, semiconductor devices, and wiring (e.g., metallization) layers formed above the semiconductor devices. The wiring layers comprise various interconnects that provide electrical connections between the devices and external connections. However, as technology scales, power density increases and a wire's ability to transfer charge to active devices diminishes due to electromigration (EM). That is, as dimensions of features (e.g., pads, wires, interconnects, vias, etc.) continue to shrink to create smaller devices, the maximum allowable current density decreases rapidly due to (EM) effects.
EM is a well known phenomenon in which, generally speaking, atoms of a metal feature are displaced due to the electrical current passing through the feature. The migration of atoms can result in voids in the feature, which can increase electrical resistance or cause failure of the feature, both of which negatively impact reliability of the integrated circuit. For example, EM damage typically originates at a location of highest current density and then progresses until a wire is broken.
Industry solutions for EM management in logic design provide few available options. And, the solutions that exist are implemented late in the design cycle, and require considerable design system support. For example, if an EM violation is observed, redesign of the circuit is required to mitigate the violations. This is a time consuming and expensive process.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.